1. Technical Field
The present invention relates to a system including two or more bus masters and a bus arbitrator for receiving requests for bus use of the bus masters to arbitrate the bus use, and more particularly, relates to an error master detector of a bus master for detecting a corresponding bus cycle error generated by the system.
2. Related Art
Computer systems and data processing systems typically use more than one bus for providing intercommunication between all internal electronic chips and other system devices such as a central processing unit (CPU), memory devices, and direct memory access (DMA) controllers that are connected to the bus. For example, a system bus is provided for system bus devices such as the DMA controller or the input/output (I/O) devices to communicate with the system memory via the memory controller. One type of system bus which has gained wide industry acceptance is the industry standard architecture (ISA) bus. Similarly, a local bus is provided for the CPU to communicate with cache memory or memory controller. An example of a local bus is a peripheral component interconnect (PCI) bus which serves as a parallel data path in addition to an ISA bus.
Typically, each standard bus has many devices attached thereto that serve as bus masters for processing data independently from the bus or other devices. A standard bus arbitrates the use of a bus regardless of a current bus cycle when another bus master requires the bus use during a bus cycle for transferring data. That is, in the standard bus, a data transfer cycle and an arbitration cycle overlap. When the arbitration cycle and the data transfer cycle are separately performed, bus occupying time of the bus master is reduced to increase performance of a system.
Bus errors which occur on a bus where the bus arbitration cycle and the data transfer cycle overlap, are classified into response errors, bus timeout errors and parity errors. Contemporary techniques for detecting bus errors and error recovery are disclosed, for example, U.S. Pat. No. 4,785,453 for High Level Self-Checking Intelligent I/O Controller issued to Chandran et al., U.S. Pat. No. 4,855,234 for Method And Apparatus For Error Recovery In A Multibus Computer System issued to Hartwell et al., U.S. Pat. No. 5,313,627 for Parity Error Detection And Recovery issued to Amini et al., U.S. Pat. No. 5,499,346 for Bus-To-Bus Bridge For A Multiple Bits Information Handling System That Optimizes Data Transfers Between A System Bus And A Peripheral Bus issued to Amini et al., U.S. Pat. No. 5,511,164 for Method And Apparatus For Determining The Source And Nature Of An Error Within A Computer System issued to Brunmeier et al., U.S. Pat. No. 5,537,535 for Multi-CPU System Having Fault Monitoring Facility issued to Maruyama et al., U.S. Pat. No. 5,588,112 for DMA Controller For Memory Scrubbing issued to Dearth et al., and U.S. Pat. No. 5,680,537 for Method And Apparatus For Isolating An Error Within A Computer System That Transfers Data Via An Interface Device issued to Byers et al. Generally, when a bus error occurs, the error type is recorded in a predetermined register, i.e., a status register, and the bus error is announced to a processor using an interrupt. In addition, a bus request signal or a bus grant signal of a bus master (error master) where an error occurs are cleared when the bus cycle begins, and the bus request signal or the bus grant signal driven by another bus master is active, i.e., a time difference occurs between the bus grant state and the actual bus. As I have observed, however, only the fact that the error occurred is announced. The bus cycle of a bus master where the error occurred is not announced. Therefore, it is impossible to rapidly repair or recover the bus master causing the bus error.